Engineering notes on ceramic substrates

DBC vs AMB: how they are made and when to use each

Both technologies put thick copper on a ceramic insulator so a power module can carry current, spread heat and isolate high voltage in one part. They differ in how the copper is attached, and that decides which ceramics you can use and how long the substrate survives thermal cycling.

Direct Bonded Copper (DBC)

Oxidised copper foil is placed on the ceramic and heated to about 1065 °C, just above the Cu–Cu₂O eutectic. A thin liquid phase wets the ceramic and bonds on cooling. There is no filler metal. The process works naturally on oxide ceramics (Al₂O₃, ZTA); AlN needs a pre-oxidised surface.

Active Metal Brazing (AMB)

Copper is brazed to the ceramic in vacuum with an Ag–Cu–Ti paste or foil at roughly 800 – 900 °C. Titanium reacts with the ceramic surface (forming TiN on Si₃N₄ and AlN), giving a strong chemical bond. AMB is the practical route for Si₃N₄ and supports thicker copper.

How to choose

• Cost-driven industrial modules: Al₂O₃ DBC.
• Better cycling without nitride cost: ZTA DBC.
• Highest heat flux: AlN AMB or DBC.
• SiC traction and long power-cycling life: Si₃N₄ AMB with 0.3 – 0.8 mm copper.

Selecting the ceramic: Al₂O₃, ZTA, AlN or Si₃N₄

The ceramic sets three things: thermal resistance through the stack, how well the substrate survives copper–ceramic CTE mismatch, and cost.

Thermal resistance

Thermal resistance of the ceramic layer scales with thickness divided by conductivity. A 0.32 mm Si₃N₄ layer at 80 W/m·K has roughly the same resistance as a 0.10 mm alumina layer would, but alumina that thin is not practical. This is why nitrides win for high power density even when their conductivity is not the highest.

Mechanical reliability

Copper expands at about 17 ppm/K. Every temperature swing loads the copper edge and the ceramic beneath it. Brittle ceramics crack and copper delaminates over time. Fracture toughness matters more than flexural strength here: Si₃N₄ at 6 – 7 MPa·m½ tolerates thick copper far better than AlN or Al₂O₃ at 3 – 4 MPa·m½.

Practical starting points

Layout design guidelines for etched copper

These are starting values for DFM. Exact limits depend on copper thickness and the manufacturer, so we confirm them on every drawing.

Rules that improve reliability

• Balance copper. Keep top and bottom copper area and thickness similar to limit warpage (camber).
• Round the corners. Use radii on copper islands instead of sharp corners, which concentrate stress.
• Add dimples or a step at the copper edge. A row of half-etched dimples near the edge reduces peel stress and extends thermal-cycling life.
• Check creepage. Gap and edge distance must also meet the creepage and partial-discharge needs of your voltage class, not only etch capability.

Reliability: thermal cycling and how substrates fail

Substrates in power modules usually fail by two mechanisms, both driven by CTE mismatch between copper and ceramic.

Conchoidal cracking in the ceramic

Cracks start under the copper edge and grow into the ceramic with each cycle. Eventually the copper lifts. Oxide ceramics with thick copper are most exposed.

Copper delamination

The bond line fails progressively from the edge. AMB bonds on Si₃N₄ resist this best.

How it is tested

• Thermal shock / cycling: typically −55 °C to +150 °C (or +175 °C for SiC), inspected by scanning acoustic microscopy (SAM) for delamination.
• Peel strength: copper-to-ceramic bond strength, in N/mm.
• Partial discharge and dielectric strength: tested at the module voltage class.

Ask us for SAM images and cycling data for the grade you are evaluating.